1. Field of the Invention
The present invention relates to a method for the simultaneous double-side grinding of a plurality of semiconductor wafers, wherein each semiconductor wafer lies such that it is freely moveable in a cutout of one of a plurality of carriers caused to rotate by means of a rolling apparatus and is thereby moved on a cycloidal trajectory, wherein the semiconductor wafers are machined in material-removing fashion between two rotating ring-shaped working disks, wherein each working disk comprises a working layer containing bonded abrasive.
2. Background Art
Electronics, microelectronics and microelectromechanics require as starting materials (substrates) semiconductor wafers with extreme requirements made of global and local flatness, single-side-referenced local flatness (nanotopology), roughness, cleanness and freedom from impurity atoms, in particular metals. Semiconductor wafers are wafers made of semiconductor materials. Semiconductor materials are compound semiconductors such as, for example, gallium arsenide or elemental semiconductors such as principally silicon and occasionally germanium or else layer structures thereof. Layer structures include for example a device-carrying silicon upper layer on an insulating interlayer (“silicon on insulator”, SOI), or a lattice-strained silicon upper layer on a silicon/germanium interlayer with germanium proportion increasing toward the upper layer, on a silicon substrate (“strained silicon”, s-Si), or combinations of the two (“strained silicon on insulator”, sSOI).
Semiconductor materials are preferably used in monocrystalline form for electronic components or are preferably used in polycrystalline form for solar cells (photovoltaics).
In order to produce the semiconductor wafers, in accordance with the prior art, a semiconductor ingot is produced which is firstly separated into thin wafers, usually by means of a multiwire saw (“multiwire slicing”, MWS). This is followed by one or more machining steps which can generally be classified into the following groups:    a) mechanical machining;    b) chemical machining;    c) chemomechanical machining;    d) if appropriate, production of layer structures.
The combination of the individual steps allotted to the groups and their order vary depending on the intended application. A multiplicity of secondary steps such as edge machining, cleaning, sorting, measuring, thermal treatment, packaging, etc. are furthermore used.
Mechanical machining steps in accordance with the prior art are lapping (simultaneous double-side lapping of a plurality of semiconductor wafers in the “batch”), single-side grinding of individual semiconductor wafers with single-side clamping of the workpieces (usually carried out as sequential double-side grinding; “single-side grinding”, SSG; “sequential SSG”) or simultaneous double-side grinding of individual semiconductor wafers between two grinding disks (simultaneous “double-disk grinding”, DDG).
Chemical machining comprises etching steps such as alkaline, acidic or combination etch in a bath, if appropriate while moving semiconductor wafers and etching bath (“laminar-flow etch”, LFE), single-side etching by applying etchant into the wafer center and radial spin-off by wafer rotation (“spin etch”) or etching in the gas phase.
Chemomechanical machining comprises polishing methods in which a material removal is obtained by means of relative movement of semiconductor wafer and polishing cloth with the action of force and supply of a polishing slurry (for example alkaline silica sol). The prior art describes batch double-side polishing (DSP) and batch and individual wafer single-side polishing (mounting of the semiconductor wafers by means of vacuum, adhesive bonding or adhesion during the polishing machining on one side on a support).
The possibly concluding production of layer structures is effected by epitaxial deposition, usually from the gas phase, by oxidation, or by vapor deposition (for example metallization), etc.
For producing exceptionally planar semiconductor wafers, particular importance is ascribed to those machining steps in which the semiconductor wafers are machined largely in a constrained-force-free manner in “free-floating” fashion without force-locking or positively locking clamping (“free-floating processing” FFP). Undulations such as are produced for example by thermal drift or alternating load in MWS are eliminated by FFP particularly rapidly and with little loss of material. FFP known in the prior art include lapping, DDG and DSP.
It is particularly advantageous to use one or more FFP at the start of the machining sequence, that is to say usually by means of a mechanical FFP, since, by means of mechanical machining, the minimum required material removal for completely removing the undulations is effected particularly rapidly and economically and the disadvantages of the preferential etching of chemical or chemomechanical machining in the case of high material removals is avoided.
The FFP obtain the advantageous features described, however, only if the methods can be carried out in such a way that a largely uninterrupted machining is achieved from load to load in the same rhythm. This is because interruptions for possibly required setting, truing or dressing processes or frequently required tool changes lead to unpredictable “cold start” influences which nullify the desired features of the methods, and adversely affect the economic viability.
Lapping produces a very high damage depth and surface roughness on account of the brittle-erosive material removal as a result of the rolling movement of the loosely supplied lapping grain. This necessitates complicated subsequent machining for removing these damaged surface layers, whereby the advantages of lapping are nullified again. Moreover, as a result of depletion and loss of sharpness of the supplied grain during transport from the edge to the center of the semiconductor wafer, lapping always yields semiconductor wafers having a disadvantageously convex thickness profile with wafer edges of decreasing thickness (“edge roll-off” of the wafer thickness).
DDG causes, for kinematic reasons, in principle, a higher material removal in the center of the semiconductor wafer (“grinding navel”) and, particularly in the case of a small grinding disk diameter, as is structurally preferred in the case of DDG, likewise an edge roll-off of the wafer thickness and also anisotropic—radially symmetrical—machining traces that strain the semiconductor wafer (“strain-induced warpage”).
DE10344602A1 discloses a mechanical FFP method in which a plurality of semiconductor wafers lie in a respective cutout of one of a plurality of carriers that are caused to effect rotation by means of a ring-shaped outer and a ring-shaped inner drive ring, and are thereby held on a specific geometrical path and machined in material-removing fashion between two rotating working disks coated with bonded abrasive. The abrasive is composed of a film or “cloth” stuck to the working disks of the apparatus used, as disclosed in U.S. Pat. No. 6,007,407, for example.
It has been found, however, that the semiconductor wafers machined by this method have a series of defects, with the result that the semiconductor wafers obtained are unsuitable for particularly demanding applications: it has thus been shown, for example, that in general semiconductor wafers result which have a disadvantageous convex thickness profile with a pronounced edge roll-off. The semiconductor wafers often also have irregular undulations in their thickness profile and also a rough surface with a large damage depth. The high damage depth necessitates complicated subsequent machining that nullifies the advantage of the method disclosed in DE10344602A1. The remaining convexity and the remaining edge roll-off lead to incorrect exposures during the photolithographic device patterning and hence to the failure of the components. Semiconductor wafers of this type are therefore unsuitable for demanding applications.
It has furthermore been shown that, in particular when using the particularly preferred abrasive diamond, the carrier materials known in the prior art are subject to high wear and the abrasion produced adversely affects the cutting capacity (sharpness) of the working layer. This leads to an uneconomically short lifetime of the carriers and necessitates frequent unproductive redressing of the working layers. It has been shown, moreover, that carriers composed of metal alloys, in particular stainless steel, such as are used in lapping in accordance with the prior art, and have an advantageous low wear in that case, are particularly unsuitable for carrying out the methods according to the invention. Thus, by way of example, the known high solubility of carbon in iron/steel in the case of the (stainless) steel carriers leads to an immediate embrittlement and blunting of the diamond that is preferably used as the abrasive of the working layer. Moreover, the formation of undesirable deposits of iron carbide and iron oxide layers on the semiconductor wafers has been observed. It has been shown that high grinding pressures, in order to constrain self-dressing of the blunt working layer by pressure-induced forced wear, are unsuitable since the semiconductor wafers are then deformed and the advantage of FFP is nullified. Moreover, the fracturing of entire abrasive grains which repeatedly occurs leads to an undesirably high roughness and damage of the semiconductor wafers. The inherent weight of the carrier leads to different degrees of blunting of upper and lower working layer and thus to different roughness and damage of front and rear sides of the semiconductor wafer. It has been shown that the semiconductor wafer then becomes asymmetrically undulatory, that is to say has undesirably high values for “bow” and “warp” (strain-induced warpage).